Device communication
This micro-controller has integrated circuitry for handling serial and parallel communication. This is facilitated by dedicated hardware-registers and instructions.
E (ENABLE) register
The 8-bit Enable register is used to control the enable state of devices attached to the serial or parallel bus lines. To this end, the register is divided into two independent four-bit groups for device selection.
Each four-bit group drives a 4-to-16 line decoder, which maps the bit pattern encoded by that group to 1 of 16 possible, mutually exclusive active-high select signals (SL0-15 and SH0-15).
Select signals SL0 and SH0 are reserved to select a NULL device ("nothing"). SL1 corresponds to the internal POR register output enable signal (SL1_PAROE). SH1 corresponds to the internal PIR register latch enable signal (SH1_PARLE). The remaining selectors can be used freely for application hardware.
Communication Registers
SOR (Serial Output Register)
A write-only parallel-to-serial shift register for serialising an output byte, modelled after a 74HC165 chip.
Writing an output value for serialisation is done by writing the value into register S.
The value is clocked out/serialized by pulsing the SCLK clock line. This happens when the SCL/SCH instructions are used repeatedly. SCL-SCH-SCL gives a posititve clock edge. SCH-SCL-SCH generates an inverted clock. Eight clock cycles are required to process a byte.
SIR (Serial Input Register)
A read-only serial-to-parallel shift register for de-serialising an incoming bit stream into an input byte, modelled after a 74HC595 chip. This is done by executing the SCL/SCH instructions repeatedly.
SCL-SCH-SCL gives a positive clock edge. SCH-SCL-SCH generates an inverted clock. Eight clock cycles are required to process a byte. Reading a deserialised input byte is done by reading register S.
POR (Parallel Output Register)
A write-only tri-state register with 8-bit parallel output, modelled after a 74HC574 chip. Writing an output byte onto the parallel bus is a two step process. First, the data byte must be latched into the register by writing it into P. Then, the register output must be enabled by selecting SL1 in the E register, as described above.
PIR (Parallel Input Register)
A read-only 8-bit parallel input register, modelled after a 74HC574 chip. Latching the current 8-bit value of the parallel bus into the register is done by selecting SH1 in E. The latched data byte can then be read from P. The bus operates in weak pull-down mode, so when all bus-devices are in tri-state mode, a zero value is registered.
Communication Instructions
The following Signal instructions contained in the SYS group operate on the communication registers:
SSI (Shift Serial In)
This instruction receives a serial bit via the serial input line. It the shifts SIR left and sets its least significant bit (LSB) to the received bit state.
SSO (Shift Serial Out)
This instruction outputs the most significant bit (MSB) of SOR onto the serial output line and then shifts SOR left.
SCH (Serial clock high)
This instruction sets the clock line to HIGH.
SCL (Serial clock low)
This instruction sets the clock line to LOW.
Parallel Communication
The Myth controller interfaces to an external bidirectional 8-bit wide bus (IO bus).
It can communicate on this bus by writing a data byte into P (POR register), and then enabling SL1 in the E register by setting its lower nybble to 1. Setting the bit to 1 switches the register from tri-state output to active output, so that the byte value is output on the bus lines.
While the output is active, other devices on the bus can read the data byte by enabling the corresponding SHx signal in E while keeping SL1 (the low-order nybble of E) set to 1.
Deselecting SL1 in E again (setting the low-order nybble to a value different from 1) tristates the POR output, so that other devices can put data bytes on the IO bus.
Enabling LH1 in E (setting the high-order nybble to 1) latches a data byte into the PIR. This byte can then be read from the P register.
Once a data byte has been read, the PIR input should be deselected again in E by setting the high-order nybble to a value different from 1.
Serial Communication
The Serial Peripheral Interface (SPI) protocol can be implemented using the device enable register E, serial registers SIR and SOR, and instructions SCL, SCH, SSI, and SSO.
Device Selection
Before communicating with a specific device connected to the serial bus, the corresponding selector bit representing the device must be set in the E register.
Data Transmission
To transmit data to the selected device, the processor writes a data byte (8 bits to be serialised for output) into the SOR (Serial Output) register.
The SSO (Serial Shift Out) instruction is then used, which clocks the serial output shift register and produces a data bit on the MOSI line. Using the instruction sequence SCL SCH SCL (Serial Clock Low/High), a positive edge clock pulse is generated.
As each bit is shifted out, it is sent to the selected device through the serial bus. The passive device processes the transmitted bit and the cycle repeats.
Data Reception
To receive data from an external device, the SSI (Serial Shift In) instruction is used. It clocks the serial input shift register, allowing the processor to receive one bit of data at a time from the selected device via the MISO line. The received data can then be read from the S register. Clocking is done as for "Data Transmission".
CPOL (Clock Polarity)
The CPOL parameter determines the idle state of the clock signal. The Myth controller provides signals SCL (Serial Clock Low) and SCH (Serial Clock High) instructions which can be used to control the clock signal's state.
To configure CPOL=0 (clock idles low), execute SCL to set the clock signal low during the idle state. To configure CPOL=1 (clock idles high), execute SCH to set the clock signal high during the idle state.
CPHA (Clock Phase)
The CPHA parameter determines the edge of the clock signal where data is captured or changed. The Myth controller provides instructions SSI (Serial shift in) and SSO (Serial shift out) to control data transfer on each clock transition.
To configure CPHA=0 (data captured on the leading edge), execute SSI before the clock transition to capture the incoming data. To configure CPHA=1 (data captured on the trailing edge), execute SSI after the clock transition to capture the incoming data.
Similarly, to transmit data on the leading or trailing edge, execute SSO before or after the clock transition, respectively.
Device Deselection
After data transmission is complete, the selected device needs to be deselected to allow other devices to communicate on the bus. This is done by updating the E register with the appropriate value.