This page describes the following instruction:
- Group: PAIR
- Mnemonic: pl
- Opcode: 242d, F2h
- Encoding: 1_111_0010b (PAIR_SRC_DST)
- Pseudo-code: ram[l][o]=pir; pc++
- P:PARALLEL L:PARALLEL
- Source is the Parallel Input register (PIR).
- Destination is the memory cell at page L offset O.
The 'P' source is a data byte received on the parallel bus. See Device Communication for how this works. The 'L' destination stores the source data byte into memory as described. See Memory Addressing for information on implied Page index registers, offset registers and so forth.